This relates generally to communications links, and more particularly, to high-speed input-output (I/O) communications links.
A typical communications link includes a transmitter (TX) module, a receiver (RX) module, and a channel that connects the TX module to the RX module. The TX module transmits a serial data bit stream across the channel to the RX module. Typical high-speed transmit data rates can be as high as 10 Gbps (gigabits per second) or more. Communications links operating at such high data rates are often referred to as high-speed serial links or high-speed I/O links.
Oftentimes, the RX module includes equalization circuitry having a continuous time linear equalizer (CTLE) and a decision feedback equalizer (DFE) that are used to provide equalization for analog signals which may have been degraded from being transmitted through a band limited channel. The CTLE is typically used to provide high frequency boosting to help cancel both pre-cursor and post-cursor long-tail inter-symbol interference. The DFE typically uses a feedback finite impulse response (FIR) filter to directly subtract out only post-cursor inter-symbol interference. Since both the CTLE and the DFE circuits perform similar functions, it may be desirable to minimize the interaction between these two circuits to avoid overcompensation.
In one conventional arrangement, the CTLE circuit is first activated during a first phase during which the DFE circuit is disabled. Once the CTLE circuit is properly initialized, the CTLE settings is fixed, and the DFE circuit can then be enabled to perform dynamic equalization during a second phase. Performing sequential equalization in two phases in this way, however, may not be optimal since the CTLE circuit does not continuously adapt to the behavior of incoming signals during the second phase.
It is within this context that the embodiments described herein arise.